Programmable semiconductor circuits form an important class of electronic components. Such circuits can be created in great number with great economies of scale for a large class of potential uses, and then can be individually customized for a given use by programming. Examples of such programmable circuits include programmable read only memories, commonly called PROMs, and programmable logic circuits, such as gate arrays and programmable logic arrays.
A PROM is a memory device in which memory cells can be selectively programmed to store bits of information. In programmable read only memories, once information has been stored it is retained without the requirement of further electrical power. This is different from standard random access memories (RAMs) which normally lose the information stored in them when power is removed. PROMs have a great variety of uses, from digital signal conversion to programming computers, and are a major type of digital electronic component.
Programmable logic devices come in several kinds. One type, called a gate array, comprises an integrated circuit having a plurality of logic gates with programmable means for selectively interconnecting them to form a desired combination of hard wired logic. Another type of programmable logic device is the programmable logic array, or PLA. A PLA normally consists of two connected intersecting matrices of lines. The first matrix, commonly called the AND plane, has a set of input lines which intersect a set of output lines, called minterms. Each of the minterm lines has a logical value equal to the binary product (or the ANDed value) of the input lines programmed to provide inputs to it. These minterm lines are supplied as inputs to an OR plane, where they intersect the set of lines which form the outputs of the OR plane, called maxterm lines. The logical value of each of the maxterm lines is equal to the binary sum (or the ORed value) of the minterms programmed to provide inputs to it. Since PLAs commonly receive not only logical variables, but also their inverse as inputs, it is possible for the outputs of the PLAs to represent not only AND and OR functions, but also, NOR, NAND and XOR functions. In addition, by latching and clocking the inputs and the outputs of a PLA, and by connecting selected outputs of the PLA to selected ones of its inputs, it is possible to make a state machine capable of cycling through a complex sequence of logical states in response to inputs supplied to the PLA. The PLA can form powerful logical devices which have many uses, from performing simple logic to driving the internal circuitry of computers.
From the above it can be appreciated that programmable devices, such as PROMs and PLAs, have many applications in digital logic design. Therefore, any advances which decrease the size or cost of such devices, or increase their performance are of great use to the electronic arts.
The assignee of the present application has previously developed programmable devices which employ antifuses as programmable circuit elements. Such antifuses have a portion of phase-change material which can be changed, by the application of a programming voltage and current, from a relatively disordered, high resistance state, to a relatively ordered or more crystalline, low resistance state. Such antifuses and programmable arrays using them are described in greater detail in U.S. Pat. No. 4,499,577 issued Feb. 12, 1985 in the names of Scott H. Holmberg and Richard A. Flasck and entitled "An Improved Programmable Cell for Use in Programmable Electronic Arrays", which is hereby incorporated by reference.
The assignee of the present application has also previously disclosed programmable circuits in U.S. Pat. application Ser. Nos. 458,919 and 558,216, filed on Jan. 18, 1983 and Dec. 5, 1983, respectively, both in the name of Robert R. Johnson and both bearing the title "Electronic Matrix Array and Method for Making the Same". These two applications, both of which are incorporated herein by reference, disclose matrix arrays in which a first set of generally parallel lines is separated from a second, crossing set of parallel lines by a selection means structure. These applications disclose a selection means structure formed of a plurality of deposited amorphous semiconductor alloy layers that function together as a diode. This diode causes current to flow between lines on opposite sides thereof so the only current path between them is at their intersection. This enables any given intersections of the lines to be uniquely addressed. The matrix arrays can also include a layer of programmable material, such as an amorphous alloy of a chalcogenide element or an amorphous alloy of silicon overlying the selection means structure. The programmable material can be programmed by, for example, the application of a programming voltage and current between a pair of crossing address lines to convert the programmable material therebetween from a relatively disordered, high resistance state, to a relatively ordered, or more crystalline, low resistance state. Thus by placing a sufficiently high voltage and current between a given line on one side of the programmable layer and a given line on the other, the portion of phase-change material located between those two lines can be converted from a relatively high resistance to a relatively low resistance state, thereby effectively programming the device and enabling the detection of the two resistance states.
The programmable devices disclosed in the four above-mentioned U.S. Pat. references have many advantages. For example, because such devices include vertical programmable cells, they enable a great density of cells to be placed within a given area. Furthermore, because such cells can be fabricated of amorphous semiconductor alloy materials, they can be fabricated at a lower cost and in multiple layers, as is disclosed in the above-mentioned U.S. Pat. application Ser. No. 458,919.